(ALU Design) Revise your design for the ALU of Exercise 1 to include 4-bit carry-lookahead logic.
Exercise 1
(ALU Design) Implement to the gate level an ALU bit slice with three selection inputs, S2, S1, S0, and a logic/arithmetic mode input, M, that implements the following 16 functions of the two data inputs A and B (and carry-in C0):
M = 0, Logic Mode | |||
S2 | S1 | S0 | ALU Operation |
0 | 0 | 0 | Fi = 0 |
0 | 0 | 1 | Fi = A XOR B |
0 | 1 | 0 | Fi = A XNOR B |
0 | 1 | 1 | Fi = A OR B |
1 | 0 | 0 | Fi = A AND B |
1 | 0 | 1 | Fi = A NOR B |
1 | 1 | 0 | Fi = A NAND B |
1 | 1 | 1 | Fi = 1 |
M = 1, Arithmetic Mode | |||
S2 | S1 | S0 | ALU Operation |
0 | 0 | 0 | Fi = not A |
0 | 0 | 1 | Fi = not B |
0 | 1 | 0 | Fi = A minus B |
0 | 1 | 1 | Fi = B minus A |
1 | 0 | 0 | Fi = A plus B |
1 | 0 | 1 | Fi = A plus 1 |
1 | 1 | 0 | Fi = B |
1 | 1 | 1 | Fi = A |
Assume a simple ripple-carry scheme between bit slices.
We need at least 10 more requests to produce the solution.
0 / 10 have requested this problem solution
The more requests, the faster the answer.