Using primitive gates, write a Verilog model of a circuit that will produce two outputs,...

Using primitive gates, write a Verilog model of a circuit that will produce two outputs, s and c, equal to the sum and carry produced by adding two binary input bits a and b (e.g., s = 1 and c = 0 if a = 0 and b = 1). ( Hint: Begin by developing a truth table for s and c.)