(Design Problem) Design a combinational circuit with three data inputs: D2, D1, D0; two control inputs: C1, C0, and two outputs: R1, R0, R1 and R0 should be the remainder after dividing the binary number formed from D2, D1, D0 by the number formed by C1, C0. For example, if D2, D1, D0 = 111 and C1, C0 = 10, then R1, R0 = 01 (that is, the remainder of 7 divided by 2 is 1). Note that division by zero will never be requested.
(a) Fill in truth tables for the combinational logic functions R1 and R0.
(b) Derive minimized sum-of-product realizations of these functions using the Karnaugh-map method.
(c) Draw a circuit schematic that implements R1 and R0 using NAND gates only. You may assume any fan-in gates that you need.
(d) Derive multilevel functions for the two outputs. Try to share subexpressions as much as possible. Do you see any advantages to a multilevel realization for this example?
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