10.3 A dynamic CMOS Read Only Memory (ROM) has been designed with a core array consisting...

10.3 A dynamic CMOS Read Only Memory (ROM) has been designed with a core array consisting of 64 rows with a pitch of 12μm and 64 columns with a pitch of 10μm as shown below. Each column is precharged to 5 V by a PMOS transistor during the interval of zero clock phase and then gets pulled down after the clock signal switches to 5 V by one or more nMOS transistors ( i.e., NOR implementation) with high gate inputs on the appropriate rows. All of the nMOS transistors have channel width W = 4 μm and the source/drain length Y = 5 μm. Now as a designer, you are to determine the propagation delay time from a particular input (on row 64) going high to a particular bit-line output (on column 64) going low t_PHL between 50% points. Assume that the input signal to row 64 becomes valid high only after the precharge operation is finished as shown in the timing diagram. Also, assume that row 64 is running over 30 nMOS transistors andcolumn 64 has 20 nMOS transistors connected to it. For delay calculation, assume that only one nMOS transistor is pulling down. Also assume that pMOS is strong enough to fully charge the precharging node during the precharge phase of the clock signal and neglect its drain parasitic capacitance. Device parameters are given:

• C_jsw = 250 pF/m

•C_jo = 80 μF/m²

•C_ox = 350 μF/m²

• L_D = 0.5 μm

• K_eq =1.0 for worst-case capacitance

• C_metal= ^2.0 pF/cm and R_metal = 0.03 Ω/sq.

• C_poly = 2.2 pF/cm and R_poly = 25 Ω/sq.

• Polysilicon line width = 2μm

• Metal line width = 2μm

• k′_n = 20 μA/V²

• k′_p = 10 μA/V²

• V _T,n = -V_T,p =1.0 V

Figure P10.3