Modify the PAL diagram of Fig. 7.16 by including three clocked D -type flip-flops betwee...

Modify the PAL diagram of Fig. 7.16 by including three clocked D -type flip-flops between the OR gates and the outputs, as in Fig. 7.19 . The diagram should conform with the block diagram of a sequential circuit. The modification will require three additional buffer– inverter gates and six vertical lines for the flip-flop outputs to be connected to the AND array through programmable connections. Using the modified registered PAL diagram, show the fuse map that will implement a three-bit binary counter with an output carry.