13.4 Since the fanout count of a typical clock signal is very high, it is important to size the interconnection wire dimensions properly. The parasitic interconnection resistance and capacitance are dicussed in Chapter 6 using formulas in (6.34), (6.36), and (6.37). The parasitic resistance in metalic wire is assumed to be 0.03Ω/square.
(a) For t=0.4 μm, h = 1 μm, l(length) = 1000 μm and w(width) = 2 μm. Calculate the interconnection delay for fanout capacitance load of 5 pF by using the Elmore delay formula. For consideration of distributed parasitic effect, the total length can be divided into 10 segments of 100-μm length.
(b) Verify the answer in part (a) using SPICE simulation.
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