Develop equations for the logical effort and parasitic delay with respect to the C0 input...

Develop equations for the logical effort and parasitic delay with respect to the C0 input of an n-stage Manchester carry chain computing C1…Cn. Consider all of the internal diffusion capacitances when deriving the parasitic delay. Use the transistor widths shown in Figure and assume the Pi and Gi transistors of each stage share a single diffusion contact.

FIGURE Manchester carry chain