The plus (+) indicates a more advanced problem and the asterisk (*) indicates that a solut...

The plus (+) indicates a more advanced problem and the asterisk (*) indicates that a solution is available on the Companion Website for the text.

*Repeat Problem 1 using the RISC CPU with data forwarding in Figure.

Figure Pipeline RISC: Data Forwarding

Problem 1

Simulate the processing of the program in Problem 2 using the RISC CPU with data-hazard stall in Figure. Give the contents of each pipeline platform and the register file (the latter only whenever a change occurs) for each clock cycle. Initially, R2 contains 0000001016, R4 contains 0000002016, R7 contains 0000003016, and the PC contains 0000000116. Is the data hazard avoided?

Figure Pipelined RISC: Data Hazard Stall

Problem 2

For the RISC design, draw the execution diagram for the following RISC program (with the contents of R7 nonzero after the subtraction), and indicate any data or control hazards that are present:

1 SUB R7, R7, R2

2 BNZ R7, 000F

3 AND R8, R7, R4

4 OR R4, R8, R2