The plus (+) indicates a more advanced problem and the asterisk (*) indicates that a solut...

The plus (+) indicates a more advanced problem and the asterisk (*) indicates that a solution is available on the Companion Website for the text.

*Write, compile, and simulate a Verilog description for the state machine diagram in Figure. Use code 00 for state STA, 01 for state STB, and 10 for state STC. Use a simulation input that passes through all paths in the state-machine diagram and include both the state and Z as simulation outputs. Correct and resimulate your design if necessary.

Figure State Machine Diagram for Problem