6.3 Consider a CMOS ring oscillator consisting of an odd number (n) of identical inverters connected in a ring configuration as shown in Fig. 6.7. The layout of ring oscillator is such that the interconnection (wiring) parasitics can be assumed to be zero. Therefore, the delay of each stage is the same and the average gate delay is called the intrinsic delay ( τP ) as long as identical gates are used. The ring oscillator circuit is often used to quote the circuit speed of a paticular technology using the ring oscillator frequency (f).
(a) Derive an expression for the intrinsic delay (τP) in terms of the number os stages n.
(b) Show that τP is independent of the transistor sizes, i.e. it remains the same when all the gates are scaled uniformly up or down.
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