A special positive-edge-triggered flip-flop circuit component has four inputs D 1, D 2,...

The first step is to write the Verilog module describing the circuit. An output register, Q, and five inputs D1, D2, D3, D4, and clk are declared as specified. Additionally, a two-bit control signal, sel, is also declared to control selection of the inputs.

An always statement, set to trigger on the rising edge of the clk signal, uses a case statement on the sel input signal to assign the value of the output Q to one of the four D inputs. The resulting Verilog code is shown below:

module uut525(Q,D1,D2,D3,D4,clk,sel);

output Q;

input D1,D2,D3,D4,clk;

input [1:0] sel;

reg Q;

always @(posedge clk)

case(sel)

2'b00 : Q <= D1;

2'b01 : Q <= D2;

2'b10 : Q <= D3;

2'b11 : Q <= D4;

endcase

endmodule

The next step is to write the Verilog test bench which will be used to simulate the flip flop. All inputs are declared using the reg keyword and all outputs are declared using the wire keyword. The system module is then instantiated with the corresponding inputs and outputs. Additionally, a first initial statement is used to create a clock signal with a period of 100 time units and a 50% duty cycle.

A second initial statement is used to set values for the four D inputs and to toggle the sel input signal through its four combinations. The final initial statement is used to terminate runtime at 500 time units. The resulting Verilog test bench is shown below:

module t_uut525;

reg D1;

reg D2;

reg D3;

reg D4;

reg clk;

reg [1:0] sel;

wire Q;

uut525 U1(Q,D1,D2,D3,D4,clk,sel);

initial begin clk = 0; forever #50 clk = ~clk; end

initial begin

D1 = 0; D2 = 1; D3 = 1; D4 = 0; sel = 2'b00;

#100 sel = 2'b01;

#100 sel = 2'b10;

#100 sel = 2'b11;

end

initial #500 $finish;

endmodule

The final step is to simulate the test bench, thus arriving at the waveform in Figure 1. The waveform shows that at every rising edge of the clk signal, the output Q is assigned the value of the D input selected by the sel signal. More specifically, Q is assigned D1, then D2, then D3, and finally D4.

Figure 1