Rewrite the VHDL given in FIGURE 12 for the 2-to-4-line decoder using (1) std_logic_vcctor notation instead of stdjogic notation for A and D_n and (2) implicit specification of the component input and output names by their order in package func_prims in library lcdf_vhdl given in the Companion Website. See FIGURE 13 and accompanying text for these concepts. Compile and simulate the resulting file as in Problem.
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