The plus (+) indicates a more advanced problem and the asterisk (*) indicates that a solut...

The plus (+) indicates a more advanced problem and the asterisk (*) indicates that a solution is available on the Companion Website for the text.

+Write a VHDL description for the sequential circuit with the state diagram given by Figure(d). Include an asynchronous RESET signal to initialize the circuit to state Init. Compile your description, apply an input sequence to pass through every transition of the state diagram at least once, and verify the correctness of the state and output sequence by comparing them to the state diagram.

Figure Construction of a State Diagram