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PADDB (Add Packed Byte Integers) is the mnemonic for an SSE SIMD instruction in the IA-32 architecture. In the RISC computer in this chapter, the equivalent instruction would add two 32-bit operands by adding the corresponding pairs of four bytes independently, one byte taken from each operand, with the result returned to the third operand, and without setting any condition codes.
(a) For operands R[SA] and R[SB] and destination R[DR], write a register transfer description of this instruction.
(b) What modifications would need to be made to the ALU in the RISC/ CISC computer to support this instruction?
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