Problem

6.4 Suppose that the resistive-load inverter examined in Exercise 6.2 is conneceted t a lo...

6.4 Suppose that the resistive-load inverter examined in Exercise 6.2 is conneceted t a load capacitance of 1.0 pF which is initially discharged. The gate of the nMOS transistor is driven by a rectangular pulse which changes from high to low at t = 0. As a result, the nMOS transistor begins to charge up the capacitor. Solve the following two parts by using the differential equations and not by using the average-current methods. The following parameters are given:

• R = 20kΩ

µn·Cox = 20 µA/V2

W/L = 15

• VT = 1.0 V

(a) Determine the 50% low-to-high delay time which is defined as the time difference between 50% points of input and output waveforms when the output waveform switches from low to high.


(b) Determine the 50% high-to-low delay time which is defined as the time difference between 50% points of input and output waveforms when the output waveform switches from high to low when the capacitor is initially charged to 5.0V.

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Solutions For Problems in Chapter 6