15.7 Design a CMOS full adder circuit and its layout using W/L=5/2 for nMOS transistors and W/L = 10/2 for pMOS transistors. For a capacitive load of 1 pF, determine the worst-case delay of your particular design when the range of power supply variations is 4.5 V to 5.5V and the operating temperature ranges from 25 °C to 85 °C. Also assume that the magnitude ranges of the threshold voltages are from 0.8 V to 1.2 V for both transistor types. All other parameters are assumed to be at their nominal values in this problem.
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