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I need the VHDL code for this pls.

Figure 1 Design a soda machine controller that can dispense two kinds of soda. If S1 Sel is selected, soda1 2. is dispensed,

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Answer #1

library ieee;
use ieee.std_logic_1164.all;

entity soda_controller is

   port (   clock :   in std_logic;
       cin1 :   in std_logic;
       cin2 :    in std_logic;
       cin3 :   in std_logic;
       S1Sel:    in std_logic;
       S2Sel:   in std_logic;
       S1out:   out std_logic;
       S2out:   out std_logic
   );

end soda_controller;

architecture arch of soda_controller is

type state is (idle, coin1, coin2, releaseS1, releaseS2);

signal present_state, next_state : state;

begin

   process (clock)

   begin
       if rising_edge (clock) then
           present_state <= next_state;
       end if;
  
   end process;

   process (present_state, cin1, cin2, cin3, S1Sel, S2Sel)

   begin
       case (present_state) is

           when idle=>   if (cin1 = '0') then
                       next_state <= coin1;
                   else
                       next_state <= idle;
                   end if;

           when coin1=>   if (cin2 = '0') then
                       next_state <= coin2;
                   else
                       next_state <= coin1;
                   end if;

           when coin2=>   if (cin3 = '0') then
                       if (S1Sel = '0') then
                           next_state <= releaseS1;
                       elsif (S2Sel = '0') then
                           next_state <= releaseS2;
                       else
                           next_state <= coin2;
                       end if;
                   else
                       next_state <= coin2;                      
                   end if;

           when releaseS1=>   next_state <= idle;

           when releaseS2=>   next_state <= idle;

           when others=>   next_state <= idle;

       end case;

   end process;

   S1out <= '1' when (present_state = releaseS1) else '0';

   S2out <= '1' when (present_state = releaseS2) else '0';

end arch;

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