CODE DETECTOR
--VHDL CODE
library ieee;
use ieee.std_logic_1164.all;
entity code_detector is
port ( clock : in
std_logic;
reset : in
std_logic;
r : in std_logic;
g : in std_logic;
b : in std_logic;
door_lock : out
std_logic
);
end code_detector;
architecture arch of code_detector is
type state is (S0, S1, S2, S3, S4, S5);
signal current_state, next_state : state;
begin
process (clock)
begin
if rising_edge (clock) then
current_state <= next_state;
end if;
end process;
process (current_state, reset, r, g, b)
begin
case (current_state) is
when S0=> if
(reset = '1') then
next_state <= S1;
elsif (r = '1' or g = '1' or b = '1') then
next_state <= S0;
end if;
door_lock <= '0';
when S1=> if (r
= '1') then
next_state <= S2;
elsif (reset = '1' or g = '1' or b = '1')
then
next_state <= S0;
end if;
door_lock <= '0';
when S2=> if (g
= '1') then
next_state <= S3;
elsif (reset = '1' or r = '1' or b = '1')
then
next_state <= S0;
end if;
door_lock <= '0';
when S3=> if (r
= '1') then
next_state <= S4;
elsif (reset = '1' or g = '1' or b = '1')
then
next_state <= S0;
end if;
door_lock <= '0';
when S4=> if (b
= '1') then
next_state <= S5;
elsif (reset = '1' or r = '1' or g = '1')
then
next_state <= S0;
end if;
door_lock <= '0';
when S5=>
next_state <= S0;
door_lock <= '1';
when others=> next_state <= S0;
end case;
end process;
end arch;
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--Simulation on ModelSim
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