Question

Write VHDL code for:

Part Ta: To Create a Clock Pre-Scaling Entity that Generates a Slow Clock Pulse Train from a Fast Clock Pulse Train: Obiective Create a Clock Pre-Scaling ENTITY called, PreScale, with one-bit input and 1-bit output The circuit is a 20-bit binary up-counter. Should roll back to zero once the max value is reached The MSB of the counter is connected to the output You may find it useful to refer to your code in Lab5 as a incrementer template to create the 20-bit Connect the most significant bit to the output, Clkout- PreScale Clkou Clki

Answer 1

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity PreScale is
   port (   Clkin   : in std_logic;
       Clkout   : out std_logic
   );
end PreScale;

architecture arch of PreScale is

signal count : std_logic_vector (19 downto 0):= X"00000";

begin

   process (Clkin)
   begin
       if rising_edge (Clkin) then
           count <= count + 1;
       end if;
   Clkout   <= count (19);
   end process;

end arch;

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Wave Tools Bookmarks File Edit View Add Format Window Help Wave -Default 4-4-4 -4 Search: Menr prescale/Cln prescale/Ckou prescale/count 00101110011111. Now 1605457900 pa 400000000 pa 800000000 ps 1200000000 pst 1600000000 ps 228758250 ps Cursor 1 228758250 ps O ps to 1685730795 ps /prescale/Ckin 1056 AM Type here to search M w: 7/8/2019