Question

Adam is delighted!!! He secured a job as a “Digital Design Engineer” in a Nuclear Power Plant. The nuclear plant has four sensors placed in four dangerous zones. These sensors indicate any impending danger which enables the maintenance officer to shut down the plant. Out of the four, three major sensors are namely X, Y, and Z. If any of the two-out of three major sensors-sense some danger, they actuate an alarm that notifies the maintenance officer for a plant shutdown. However, there is a small caveat. If sensor Z is one of the two major sensors that triggered an alarm, the maintenance officer shuts the plant only if another sensor (minor), “sensor B”, associated with sensor Z also sounds the alarm. Adam had to dust his Boolean algebra skills to design the truth table that outputs a variable S which indicates when the plant has to shut down. He also has to provide a schematic capture of the same that helps the maintenance officer to understand the conditions for the plant shutdown. Imagine "U" were Adam, and provide a viable solution. Pre-lab work: 1. Draw the Boolean Logic Network for above problem statement 2. Write the truth table for the same. 3. Specify the type of gate and quantity for question 1 5. What is the significance of Xilinx Design Constraints file (XDC) in generating a programming file?

please # them for each of the problem, so i can read it carefully (organize please!)

Answer 1

Output

2. Major sensors x, 12. If alongwith any other major Sensor triggers on alarm, a office only shuts down 2 العمل وجبه عن في شي ( م منهما x les lz 18 Alarm Triggon Cruje rojo know enor) 77 0-00-0 True only y y are both or xhal & are or YR 2 RB are 1 1 |-|-|-|-|--|-- . | olololo ole 2 --OO--- - -D - 10

3. Type of gates gates us yed are: AND OR GATE GATE (3) (1)

5.

XDCs are not just simple strings; they are Tcl commands that the Vivado Tcl interpreter sequentially reads and parses. You can enter design constraints in several ways at different points in the design flow. You can store XDCs in one or more files that can be added to a constraint set in Vivado Project Mode, or read the same files directly into memory using the read_xdc command in Non-Project mode.The Vivado Design Suite synthesis and implementation tools are timing driven. Having accurate and correct timing constraints is vital for meeting design goals and ensuring correct operation. Because the Vivado tools are timing driven, it is important to fully constrain a design, but not over-constrain, or under-constrain it. Over-constraining a design can lead to long run-times and sub-optimal results because the tool can struggle with unrealistic design objectives.Under-constraining a design can cause the Vivado tools to perform unnecessary optimizations, such as examining paths with multicycle delays or false paths, and prevent focus on the real critical paths.