Question

1. (15 pts) For the following C statement, what is the corresponding MIPS assembly code? Assume f, g, h correspond to $80, $s1, and $s2, respectively. f=g+(h-5) 2. (15 pts) For the following pseudo-MIPS assembly instructions, what is the corresponding C code? add f, g, h add f,i, f 3. (30 pts) Provide the instruction type, assembly language instruction, and binary representation of the instruction described by the following MIPS fields: a. op = 0, rs = 18, rt=9, rd = 20, shamt = 0, funct=34 (15pts) b. op.= 43, rs = 11, rt=18, address=1000 (15pts)

Answer 1

Answer is as follows :

Answer 1 :

MIPS Code for given C statement :

lui $a1 , 5 // we don't subtract immediate value, so we temporary loads the data 5 to register $a1.

sub $s2, $s2 , $a1 // it will perform the (h-5) and store result back to h

add $s1, $s1 , $s2 // it will perform (g+h) where h is updated from last instruction and store result to g

sw $s1 , 0($s0) // calculated result in g stored to register $s0 i.e. consider as variable f

Answer 2 :

#include <stdio.h>

int main()
{
int f,g,h,i ; // intialize variables
int temp ; // temporary variable
f = g+h ; // perfrom "add f,g,h" instruction
f = i+f ; // perfrom "add f,i,f" instruction
  

return 0;
}

Answer 3 :

Part A :

opcode = 0 = 000000 (6 bits opcode)

rs = 18 = 10010 (source register 1, "5 bits") , equivalent to register $s2

rt = 9 = 01001 (source register 2, "5 bits") , equivalent to register $t1

rd = 20 = 10100 (destination register, 5 bits) , equivalent to register $s4

shamt = 0 = 00000 (5 bits shamt)

funct = 34 = 100010 (6 bit funct)

So the opcode is 0, the instruction is R-Type instruction

funct 100010 is used for SUB instruction, so instruction is SUB $s4 , $s2 , $t1

Binary Representation order is opcode -> source reg 1 -> source reg 2 -> destination reg ->shamt -> funct,

So binary representation is : 0000 0010 0100 1001 1010 0000 0010 0010

Part B :

opcode = 43 = 101011 (6 bit)

rs = 11 = 01011 (source register 1 , "5 bits") , equivalent to register $t3

rt = 18 = 10010 (source register 2, "5 bits") , equivalent to register $s2

address = 1000 (memory address 16 bits) , 0001 0000 0000 0000

So opcode is 43 or 101011 i.e. SW instruction used for storage. So it is I- Type instruction

MIPS SW instruction is : SW $s2 , 1000($t3)

Binary Representation order is opcode -> source reg 1 -> source reg 2 -> address

So binary representation is : 1010 1101 0111 0010 0001 0000 0000 0000

As HOMEWORKLIB Guidelines, we can only answer to four question including sub parts. So i answer four question i.e. Question 1, 2 and 3 (2 parts). So please repost the question 4. It would be helpful

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