We find a way of improving the floating point instruction performance of a machine and make it run 15 times faster.
Time can be defined in different ways, depending on what we are measuring: Response time : The time between the start and completion of a task. It includes time spent executing on the CPU, accessing disk and memory, waiting for I/O and other processes, and operating system overhead. This is also referred to as execution time. Throughput :The total amount of work done in a given time. CPU execution time : Total time a CPU spends computing on a given task (excludes time for I/O or running other programs). This is also referred to as simply CPU time.
cycle time=1.5 time
speed up =4
improvement=4*1.5=9
I am explaining you all the details
with an example
machine A runs a program in 20 seconds machine B runs the same program in 25 seconds how many times faster is machine A? 25 20 = 1.25
Comparing Machines Metrics Execution time Throughput CPU time MIPS – millions of instructions per second MFLOPS – millions of floating point operations per second Comparing Machines Using Sets of Programs Arithmetic mean, weighted arithmetic mean Benchmarks
The clock cycle time is the amount of time for one clock period to elapse (e.g. 5 ns). The clock rate is the inverse of the clock cycle time. For example, if a computer has a clock cycle time of 5 ns, the clock rate is: 1 ---------------------- = 200 MHz 5 x 10-9 sec
We find a way of improving the floating point instruction performance of a machine and make...
You look at compilers as a way to improve performance. Your outdated compiler produces an instruction count of 2 times 10^9 instructions which execute in 1.3 sec. a) What is the average CPI of the program if the clock period is 0.5 ns? b) A new compiler generates only 1 times 10^9 instructions, with a CPI of 1.2. On the same processor (same clock), what speedup does the new compiler produce?
A processor is designed such that the clock of the processor runs at 1 GHz. The following table gives the instruction frequencies for the benchmark and how many cycles each instruction takes. Instruction Type Frequency Cycles Load & Stores 25% 10 cycles Arithmetic Instructions 65% 6 cycles Branch instructions 10% 4 cycles (a) Calculate the CPI for the above benchmark. (b) Suppose the amount of registers are doubled, such that clock cycle time increases by 40%. What is the new...
Problem 3. (25 pts.) Compilers can have a profound impact on the performance of an application. Assume that for a program, compiler A results in a dynamic instruction count of 1 billion instructions and has an execution time of 1.1 seconds, while compiler B results in a dynamic instruction count of 1.2 billion instructions and an execution time of 1.5 seconds. A) Find the average CPI for each program given that the processor has a clock cycle time of 1...
Make sure to show how you solved the problem step-by-step: Consider three different processors P1, P2, and P3, executing the same instruction set. P1 has a clock cycle time of 300 picosecond and a CPI (clock cycles per instruction) of 1.5. P2 has a clock cycle time of 400 picosecond and a CPI of 1.0. P3 has a clock cycle time of 250 picosecond and a CPI of 2.0. P1 is running a program with 10 instructions. P2 is running...
Assume that for a program, compiler A results in a dynamic instruction count of 8.0E8 and has an execution time of 2.4 s, while compiler B results in a dynamic instruction count of 1.25E9 and an execution time of 1.8 s. a. [10] Find the average CPI for each program given that the processor has a clock cycle time of 2 ns. b. [10] Assume the compiled programs run on two different processors. If the execution times on the two...
Please Solve 1(c). itby important Q. Disc uss the features of RISC and CISC Architecture. dware implementations Mt &t M2 of the same instruction set. There are three classes F, I & N of instructions in the instruction The average CPl for the three instructi Class set. Miclock rate is 600 MHz, M2's clock cycle is 2ns. on classes on M1 & M2 are as follows: Comments Floating Point Integer Arithmetic Non-arithmetic CPI for M 5.0 2.0 2.4 CPI for...
Given a processor that runs at 1GHz with the following: Instruction-------------- Frequency --------------Cycles Load & store ----------------25% --------------------10 arithmetic instructions------ 65% --------------------6 branch instructions -----------10%-------------------- 4 1) Calculate the CPI for the above. 2) Suppose the amount of registers are doubled, such that clock cycle time increases by 40%. What is the new clock speed (in GHz)? 3) Assume only the load & stores instructions are speed up by 5 times and their frequency is increased to 50% (Arithmetic instructions...
Topics 1. MIPS instruction set architecture (ISA). 2. Performance. 3. MIPS datapath and control. Exercise 1 Consider the memory and register contents shown below. Registers Ox0100 FFF8 13 ($t 5) 14 ($t6) 0x0100 FFFC 0x0101 0000 Memory 0x0000 0000 0x0001 1100 0x0A00 со00 0x1234 4321 OxBAOO OOBB 15 OXAAAA 0000 0x1111 1010 0x7FFF FFFD 0x0100 FFFO 0x0101 0008 (St7) Ox0101 0004 16 ($80) 0x0101 0008 17 ($sl) Show what changes and give the new values in hexadecimal after the following...
(e) Suppose we measure the code for the same program from two different compilers and obtain the following data. Assume clock rate is 3GHz, which code sequence will execute faster according to execution time? or According to MIPS? By how much? (25 pts CPI for Instructions Code from Instruction Count (billions) CPI Compiler 1 Compiler 2 9 1 3 (e) Suppose we measure the code for the same program from two different compilers and obtain the following data. Assume clock...
Base machine has a 2.4GHz clock rate. There is L1 and L2 cache. L1 cache is 256K, direct mapped write through. 90% (read) hit rate without penalty, miss penalty is 4 cycles. (cost of reading L2) All writes take 1 cycle. L2 cache is 2MB, 4 way set associative write back. 95% hit rate, 60 cycle miss penalty (cost of reading memory). 30% of all instructions are reads, 10% writes. All instructions take 1 cycle - except reads which take...