Question

Design a PLA like a ROM.

A programmable logic array (PLA) performs the same basic function as a ROM. A PLA with n inputs and m outputs can realize m functions of n variables. The internal organization of the PLA is different from that of the ROM. The decoder is replaced with an AND array which realizes selected product terms of the input variables. The OR array ORs together the product terms needed to form the output functions, so a PLA implements a sum-of-products expression (as shown in an Example Problem of Figure 9-29, page 276 of your TEXT), while a ROM directly implements a truth table. Design a PLA that would perform the same function of the ROM of Q1. Draw a detailed diagram of your design showing the switching devices clearly as shown in Figure 9-229 (page 276) of your Text.

Answer 1

Inputs A' В' A'B' +V +V +V AC BC AC +V 0 F1 F Outputs Fig 9 -PL A with 3 inputs, 5 product t ems and 4 outputs

FO 2n(0,1,4,6)- A'B'+AC F1 Σ1n(2.3.4.6.7) = B+AC" F2 - Zm(0,1,2,6) -A'B'+BC' F3- Žm(2,3,5,6,7) AC+B im m(2,5 The above set of formulas are implemented using NOR-NOR logic of PLA a shown in Fig. 9 by placing the NMOS switching transistors wherever the connection has to be established. The same set of equations can be implemented using an AND-OR array equivalent as shown in Fig. 10

OR AND Fig 10-AND-OR array equivalent of Fig. 9 The contents of a PLA can be specified by a modified truth table as shown in Fig.11. The input side of the table specifies the product terms . The symbols 0,1 and indicate whether a variable is complemented, not complemented or not present in the corresponding product term. The output side of the table specifies which product tems appear in which output function. A 1 or 0 in the output terms indicate whether a given product term is present or not present in the corresponding output function

Inputs Outputs ProductA B CIFO F1 F2 F3 A'B AC 0 1 0 1 BC AC fig II - PLA Table for Fig. lt0 The first row of the table indicates that the term A'B is present in output functions F0 and F2. The second row indicates that AC is present in F0 and F1 This PLA table can be written directly using the given set of equations to be realized using PLA logic. Realization of a given function using min number of rows in the PLA

F1=Σm(2,3,5,7,8,9, 10,11,13,15) F2= Σm(2,3,5,6,7,10,11,14,15) F3-m(6,7,8,9,13,14,15) (1) abd ab'c ab ab ab cd 00 01 1 1 Λ0/ cd 00 01 11 10 \ cd 00 01 11 \10 01 01 01 10 10 F3 a'bd Fig 12 - Multiple Output Kamaugh Map F1 =BD-B,C+AB' (4) F2 = C+ABD (5)

PLA Realization of Equations Inputs a'bd ab b'c Word Lines bc Outputs Fig 14-PLA Realization of Equations 7, 8 and 9. Fig 14 shows the PLA structure, which has four inputs, five product tems and three outputs as shown in equation 7.8 and 9. A dot at the intersection of word line and an input or output line indicates the presence of a switching element in the array