Question

PROBLEM 5: (20 pts) Given the figure and System Verilog code below, answer the followinsg questions about the recister ile. nodule regtileCinput logic clk, input 1ogie 3, iaput logic (3:)rai, ra2, wa3, input logic t3i:0] was, r15, output logic (31:0) rd1, rd2) CLK A1 WES A2 RD1 logic (31:0) rtt1s:o) RD2 always.ff (posedge clk) - АЗ Register WD3Fille R15 entnodule Part A (5 pts) List the input values that would allow R10 to be read. Put an "X" for the value of inputs that do not matter. ral ra2 = r15 clk Part B (5 pts) How many bits is WD3 Part C (5 pts) List the input values that would allow R12 to be written to. Put an "X" for the value of inputs that do not matter. ra2 ra3 . we3 Part D (5 pts) List the output values that would occur if ral 5, ra2 - 3, ra3 6, wd3 1527, r15 10000, and we -0. Assume the clock has received the appropriate inputs for 1 clock cycle. Page 6 of 8