Question

AIM: Write a VHDL code for IC7474a positive edge triggering D flip flop. TITLE: IC7474a positive edge triggering D flip flop. CIRCUIT DIAGRAM: pr_jb clr_1 D clk D Qn D

Answer 1

Here I am providing the code. Hope it helps.

VHDL Code

First problem

library ieee;
use ieee. std_logic_1164.all;

entity D_FF is
PORT( D,CLOCK: in std_logic;
Q: out std_logic);
end D_FF;

architecture behavioral of D_FF is
begin
process(CLOCK)
begin
   if(CLOCK='1' and CLOCK'EVENT) then
       Q <= D;
   end if;
end process;
end behavioral;

Thank you for the question. If any doubts please comment me.