Question

• After 4 CLK pulse, specify the value of A-Reg, B-Reg, and D-FF for the following serial adder circuit, if A-Reg is initialized by 1110, B-Reg is initialized by 1011 and D-FF is reseat at the beginning? (Fig. 14) A-Reg 1 1 s 0 F.A 1bit С 0 1 1 0 1 B-Reg D clk B-Reg 1 1 1 A-Reg 1 1 0 A. B. C. E. 0 1 1 1 0 1 1 1 OOOO olololo ololo D-FF 1 0 1 1 0 0 O 1 1 0 0 Fig. 14 Line A on the table OB. Line B on the table c. Line Con the table Line D on the table D. None of them E.

Answer 1

The given circuit A-Reg - 0 s FA Ibit - 0 B-Reg we need Truth tables Adder and Deflipflop. for bath Full D- CE Truth tabli B Q+ Q7 o

Full adder Truth tabli Inputs outputs i, io Ci-1 S; C; O I O 0 O - O - O since D-R is reset at the beginning carry initial iso, the 2011owing table and carry for sum gives outputs Certain clks clk inputs in C;-) outputs Ci $i D-FF . 0 3 1 ។ 1 1

しいし、 can see A-reg From digure is shifted iwith Sum bits, values or Sum o • AP .. Aing has after 4.clks Aireg : Tool Also 13-reg is Shitted with ó after every clk pulse. CB-reg SOOO Also D-rf ile is since the carry is generated after (from above :D-FR1) 4th elk pulse table). 2 from ginen dig 14 is corneet, line c on the table . Option 'C' is correnti