Answer Given that a) General format for addressing models in MSP430 As sem blue Addressing mode As/Ad 0010 0110 Oil1 0111 101- ill- : Register mode Indexed mode symbolic mode Absolute mode Indirect register mode Indirect auto increment model 1. Immediate mode for blw means byte/word. For byte value is I and for word, the volue is o. For instruction " add.w #Ox 0055, R6": It is a double operand Hexadecimal value. 50360055 Binary value 0101 0000 0011 0110 0000 0000 0101 0101 Explanation General for for add instruction opcode s-reg 0101 0000 1/4-bits) 1.64-bits) Ad register 0 (1-bit) blw As register Dureg R6 (-bit) (2-bits) curbits) Op code Screg 0101 0000 Cu-bits) Cu-bits) Ad register blo As register D-reg . 0 1 10110 (-bit) (1-bit) (2-bits) 1(4- bils)
The instruction means "add.w#ou0055 ,RO" moves the ] Ox ooss into register R6. so destination register Dareg is Ro and source register S-reg iso. It is an immediate addressing mode so ASIAd value is 110. Hence, the binary value is 0101 000 0011 0110. For instruction" mov.w RG, R7" :- It is a double operand Hexadecimal value: 4607 Binary value OIDO 0110 0000 0111 Explanation:- General format for mov instruction:- op code s-reg Ad register blow As register Dreg olon | RG | o | o | oo 87 cu-bits) Cu-bits) Ci-bit) (-bit) (2-bits) (4-biky Top code s- reg Ad register blo As register | D-reg) | 0100 01100 0100 01 cu-bits) (u-bits) Ci-bit) Cl-bit) | (2-bits) cu-bis) The instruction means "mov.w R6, R7"moves the value of RG into register R7. So, the source register S-reg is R6 and the destination register D-reg is R1. It is a register addressing mode. So Aslad
For instruction Pre R6")- It is a single operand Hera decimal value: 1006 Binary value :0001 0000 0000 0110 Explanation:- General format for the instruction. Op code I b'w Ad register | Dereg | 0001000000 . 0 .RG (9-bits) Ci-bit) | Cl-bit) [4-bits)| L OP code il blw 1 000100000 0 1 (9-bits) | Combit) Ad register | D-reg ! 0 / 0110 (1-bit) ] (u-bits) the instruction means "vye R6" rotate right content of register RG. so, the destination register Doreg is RG. Hence, the binary value is 0001 0000 0000 0110. For instruction imp Main loop":- It is jump instruction Hexadecimal value : 3FFA Binary value : 00011 1011 1111 1010 Explanation- General form for sump instruction: Opcode 001 (3-bits) condition hiobit two's complement PC offset !!! 1111111010 I (3-bits) L (10-bits)
28 Disassembly X Memory Browser Mainloop: cena: 5036 0055 ADD.W #exe055, R6 frov. R6, R7 ceee: 4607 MOV. R6,BZ rrc R6 c010: 1006 RRC R6 3e rrc R6 c012: 1006 RRC jmp Mainloop c014 3FFA JMP (Mainloop) Mali 29 New PC = c014-c00a = -6 R6
let's jo's bit z's complement of G:- 10 bits of 6 = 00 0000 0110 is complement of 6 =11llll 1001 Add 1 = lo bits 2's compliments ll.llll 1010 (PC offset) Hence, binary value 001 !!! on 1010. 5) for instruction "add.w#0X0055, R6": It is a double speed operand. Opcodes-reg Ad register blos As register D-reg. I 0101 0000 0 1 0 1 0110 (u-bits) (u-bits) (l-bit) (l-bit) (2-bits) |cu-bits) For instruction "mov.co RG, R7":- It is a double operand Copcode Is-reg Ad register blw As register org] | 0100 0110 0 0 00 101 curbits) (u-bits) Crabil) (-bit) (2-bits) curbity For instruction "rre RG":- It is a single operand. I Ad register D-reg - Op code I blo 0001000000 ca-bits) I Clobit) 0110 crobit) (u-bits)
for instruction "jump Main loop":- It is jump instruction Pc effect I opcode condition / co-bit two's complement 001 11 illl 11010 | (3-bits) (3.6its) | (10-bits)