Question

Implement the following statements using MS430 assembly instructions. You may use more than one, but you should minimize the number of instructions required. You can use both native and emulated instructions. Use hex notation for all numbers 1. (a) Move the word located in register R14 to R15 (b) Increment the word in R6 by 2. (c) Perform a bitwise ANDing of the word located at address 0x0240 with the datum in R15, placing the results in R15. (d) Rotate the contents of register R4 arithmetically to the left by two places. (e) Test the word located at address 0x0210 to see if the LSB (least significant bit) s set. If it's not set, jump to the label called loop. Else do nothing. (f Compare the word located at address 0x0200 to a word whose address is 32 bytes beyond the address contained in R15. If the carry bit is set after the comparison, clear all bits in R15. Table 3 Single Operand Instructions 15 14 13 12 11109 DIS Register 9-bit O Mnemonic RRC SWPB RRA SXT PUSH CALL RETI Roll dst right through C Swap bytes Roll destination right Sign extend destination Push source on stack Subroutine call Return from interrupt 0 001 0 0 0 01 Swap bytes 0 0 0 1 0 0 0 1 10Z bit 7-+bit 8...bit 15 0 | 0 | 0 | 1 0 | 0 | 1 | 0 | 0 --|-|- Sp.2+SP, src→@SP 0 | 0 : 0 | 1 ⓞ 0 | 1 | o l 1 -| SiP-2→SP, PC+2+@SP, dst→PC o i 0 | 0 | 1 0 | 0 | 1 | 1 | 0 · ㄧ · 1 · I + @SP+→SR, @SP+→PC 15 14 13 12 11 10 Mnemonic JNZIJNE 0 0 1 0 0 0-Jump if not equal JZIJEQ JNCIJLO JCIJHS ode Jump if equal 0 : 0.110| 1-01-1-1-. Ol Jump if carry flag equal to zero 0 0 1 0 11 0 0 11 00-1Jump if negative (N 1) 0011 01.Jump if greater than or equal (N V) 1 Jump if carry flag equal to one JGE JL JMP ng· ー-1-1Jump if lover (NzV) 0 011 11-Unconditional jump Table 5. Double Operand Instructions 15 14 13 12 11 10 4-bit Opcode Source Register Ad b/w Destination Register MOV ADD ADDC SUBC SUB CMP DADD BIT Move source to destination Add source to destination Add src and C to dst Subtract src and NOT C from dst Subtract source from destination Compare source to destination Decimal add src and C to dst Test bits in destination Clear bits in destination Set bits in destination XOR source with destination AND source with destination 1 0 00 dst+ not.src+1-+dst 1 | 0 | 1 | 1 0 ! z src.and.dst 00---not.src.and.dst-+dst 1 1 01 -src.or.dst-+dst 11 1 0 z src.xor.dst-+dst BIS XOR AND Status Register: bit affected, - bit not affected, 0 cleared, 1 set, z same as Z gisterAs Addr Mode Syntax Constant Remarks R2 R2 R2 R2 R3 R3 R3 R3 Register x(R2 Register mode )Absolute address mode, next word contains addres 0x0004+4 R3 0x0000 0 0x0001 +1, No extension word 01 0x0002 2 0xFFFF-1 #-1 | Table 1. Source Addressing Modes (As) Address Mode Register Syntax Operation As Registers 00 RO-R2, R4-R15 Rn 00 R3 Register Contents 0 Constant #0 addr-(PC+nextword) pointsto operand Symbolic 01 RO (x(PC)) Indexed Absolute R1, R4-R15 x(Rn) (Rn+x) points to operand. x is next code word 01 R2 01 R3 &addr #1 Next code word is the absolute address. (x(SR)) | +1 Constant Indirect 10 RO-R1 R4-R15@RnRn points to operand 10 R2 10 R3 11 RO 11 R1,R4-R15 11 R2 11 R3 +4 Constant +2 Constant #2 Immediate Indirect auto-ind | #N | Next word is the constant N. (@PC+) @Rn+ Rn points to operand, Rn is incremented (1 or 2) | #8 | +8 Constant 1 Constant #-1 Bits 4 and 5 in Single (Table 3) and Double (Table 5) Operand Instructions Table 2. Destination Addressing Modes (Ad) Address Mode Register Symbolic Indexed Ad Registers 0RO-R2, R4-R15Rn 0 R3 1 RO 1 R1, R4-R15 Syntax I #0 addr Operation Register Contents Bit bucket (PC+next word) points to operand. (x(PC)) | (Rn+x) points to operand. x is next code word 5-(Rn) 1 R2 &addrNext code word is the absolute address. (x(SR)) Absolute Bit 7 in (Table 5) Operand Instructions

Answer 1

Answer :- a.) MOV.W @R14, R15

Answer :- b.) INCD.W R6 ; INCD increases the value by 2.

Answer :- c.) MOV #0x0240, R14
AND.W @R14, R15

Answer :- d.) RLA R4
RLA R4

Answer :- e.) MOV.W #0x0210, R14
MOV.W @R14, R15
AND.W #0x0001, R15
JNZ loop

Answer :- f.) MOV.W #0x0210, R13
MOV.W @R13, R14
MOV.W 32(R15), R5
CMP.W R14, R5
JNC skip
CLR.W R15
skip : ...