MARIE Assembly Code Problem For the following problem, please create new MARIE instructions by pr...
MARIE Assembly Code Problem
For the following problem, please create new MARIE instructions by providing the full MARIE RTN (register transfer notation) for the described operation. Your answer should include the fetch, decode, operand fetch (if necessary), execution and store result (if necessary) stages. When you see X in these instructions, this is a main memory address (the last 12 bits of the 16-bit instruction) – refer to this as IR[11..0] and not X.
Problem:
LoadZero X – this is a conditional instruction, if the AC currently stores the value 0, then load the datum at memory location X
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MARIE Assembly Code Problem For the following problem, please create new MARIE instructions by pr...
MARIE Assembly Code Problem For the following problem, please create new MARIE instructions by pr...
MARIE Assembly Code Problem For the following problem, please create new MARIE instructions by providing the full MARIE RTN (register transfer notation) for the described operation. Your answer should include the fetch, decode, operand fetch (if necessary), execution and store result (if necessary) stages. When you see X in these instructions, this is a main memory address (the last 12 bits of the 16-bit instruction) – refer to this as IR[11..0] and not X. Also, assume there is an additional...
MARIE Assembly Code Problem For the following problem, please create new MARIE instructions by pr...
MARIE Assembly Code Problem For the following problem, please create new MARIE instructions by providing the full MARIE RTN (register transfer notation) for the described operation. Your answer should include the fetch, decode, operand fetch (if necessary), execution and store result (if necessary) stages. When you see X in these instructions, this is a main memory address (the last 12 bits of the 16-bit instruction) – refer to this as IR[11..0] and not X. Problem: ClearIndirect X – X is...
MARIE Assembly Code Problem For the following problem, please create new MARIE instructions by providing the...
MARIE Assembly Code Problem For the following problem, please create new MARIE instructions by providing the full MARIE RTN (register transfer notation) for the described operation. Your answer should include the fetch, decode, operand fetch (if necessary), execution and store result (if necessary) stages. When you see X in these instructions, this is a main memory address (the last 12 bits of the 16-bit instruction) – refer to this as IR[11..0] and not X. Problem: ClearIndirect X – X is...
For questions 3-4, provide the full MARIE RTN (register transfer notation) for these new MARIE operations....
For questions 3-4, provide the full MARIE RTN (register transfer notation) for these new MARIE operations. Your answer should include the fetch, decode, operand fetch (if necessary), execution and store result (if necessary) stages. When you see X in these instructions, this is a main memory address (the last 12 bits of the 16-bit instruction) – refer to this as IR[11..0) and not X in your RTN. 3) AutoIncrLoad X - the autoincrement addressing mode is used to access a...
[20 pts] 5- Consider the following hypothetical 1-address assembly instruction called "Store Accumulator Indirect with Post-increment"...
[20 pts] 5- Consider the following hypothetical 1-address assembly instruction called "Store Accumulator Indirect with Post-increment" of the form STA (x)- : M(M(x)) ← AC, M(x) ← M(x)+1 Suppose we want to implement this instruction on the pseudo-CPU discussed in class augmented with a temporary register TEMP. An instruction consists of 16 bits: A 4-bit opcode and a 12-bit address. All operands are 16 bits. PC and MAR each contain 12 bits. AC, MDR, and TEMP each contain 16 bits,...
b. A microprocessor has an instruction set that consists of 117 instructions, which need fetch, decode, read operand, execute, write and interrupt stages. Assume that as an average, each stage requir...
b. A microprocessor has an instruction set that consists of 117 instructions, which need fetch, decode, read operand, execute, write and interrupt stages. Assume that as an average, each stage requires three micro- operations to complete. Also, assume that the control memory is N bits wide (i.e., control field bits + address selection field bits + address-one bits + address-two bits N bits). The control field bits are 15 and there are 15 flags to be monitored. i. How many...
RISC machines than in superscalar processuIS. (c) Show the pipeline activity for the following code fragment with a...
RISC machines than in superscalar processuIS. (c) Show the pipeline activity for the following code fragment with and without applying the delayed branch technique. Assume that there are three pipeline stages (fetch-decode, address calculation, data movement) for load and store instructions and two stages (fetch-decode, execute) for ALU instructions. Address Instruction Comment 100 LOAD RA,X X ->RA 101 LOAD RB,Y ADD RA,RB RA RB -> RA 102 103 104 JUMP 106 ADD RB,1 STORE Y, RB STORE X,RA RB-> Y...
2. (a) Briefly describe the compiler-based register optimization technique (typically (4 marks) (b) Describe the delayed branch technique and explain why it is more common in (4 marks) tetch, ind...
2. (a) Briefly describe the compiler-based register optimization technique (typically (4 marks) (b) Describe the delayed branch technique and explain why it is more common in (4 marks) tetch, indirect and moon used for RISC machines). (c) Show the pipeline activity for the following code fragment with and without applying the delayed branch technique. Assume that there are three pipeline stages (fetch-decode, address calculation, data movement) for load and store RISC machines than in superscalar processors. instructions and two stages...
Implement the following statements using MS430 assembly instructions. You may use more than one, ...
Implement the following statements using MS430 assembly instructions. You may use more than one, but you should minimize the number of instructions required. You can use both native and emulated instructions. Use hex notation for all numbers 1. (a) Move the word located in register R14 to R15 (b) Increment the word in R6 by 2. (c) Perform a bitwise ANDing of the word located at address 0x0240 with the datum in R15, placing the results in R15. (d) Rotate...
1. One of the reasons why the MARE architecture is very inefficient is because it only has 1AC As...
I
need answer for qustion (2)
1. One of the reasons why the MARE architecture is very inefficient is because it only has 1AC Assuming that you have access to many other ACs (AC, AC1, AC2, etc) Assume that in the new MARIE Architecture, you can do ADD 105 AC1 This means: Value @ x105 ACAC or suB 104 AC2 → This means: Valus @ x 104 + AC → AC2 How would your program (Lab #s, Question 1, also...
For questions 3-4, provide the full MARIE RTN (register transfer notation) for these new MARIE operations. Your answer should include the fetch, decode, operand fetch (if necessary), execution and store result (if necessary) stages. When you see X in these instructions, this is a main memory address (the last 12 bits of the 16-bit instruction) – refer to this as IR[11..0) and not X in your RTN. 3) AutoIncrLoad X - the autoincrement addressing mode is used to access a...
[20 pts] 5- Consider the following hypothetical 1-address assembly instruction called "Store Accumulator Indirect with Post-increment" of the form STA (x)- : M(M(x)) ← AC, M(x) ← M(x)+1 Suppose we want to implement this instruction on the pseudo-CPU discussed in class augmented with a temporary register TEMP. An instruction consists of 16 bits: A 4-bit opcode and a 12-bit address. All operands are 16 bits. PC and MAR each contain 12 bits. AC, MDR, and TEMP each contain 16 bits,...
b. A microprocessor has an instruction set that consists of 117 instructions, which need fetch, decode, read operand, execute, write and interrupt stages. Assume that as an average, each stage requires three micro- operations to complete. Also, assume that the control memory is N bits wide (i.e., control field bits + address selection field bits + address-one bits + address-two bits N bits). The control field bits are 15 and there are 15 flags to be monitored. i. How many...
RISC machines than in superscalar processuIS. (c) Show the pipeline activity for the following code fragment with and without applying the delayed branch technique. Assume that there are three pipeline stages (fetch-decode, address calculation, data movement) for load and store instructions and two stages (fetch-decode, execute) for ALU instructions. Address Instruction Comment 100 LOAD RA,X X ->RA 101 LOAD RB,Y ADD RA,RB RA RB -> RA 102 103 104 JUMP 106 ADD RB,1 STORE Y, RB STORE X,RA RB-> Y...
2. (a) Briefly describe the compiler-based register optimization technique (typically (4 marks) (b) Describe the delayed branch technique and explain why it is more common in (4 marks) tetch, indirect and moon used for RISC machines). (c) Show the pipeline activity for the following code fragment with and without applying the delayed branch technique. Assume that there are three pipeline stages (fetch-decode, address calculation, data movement) for load and store RISC machines than in superscalar processors. instructions and two stages...
Implement the following statements using MS430 assembly instructions. You may use more than one, but you should minimize the number of instructions required. You can use both native and emulated instructions. Use hex notation for all numbers 1. (a) Move the word located in register R14 to R15 (b) Increment the word in R6 by 2. (c) Perform a bitwise ANDing of the word located at address 0x0240 with the datum in R15, placing the results in R15. (d) Rotate...
I
need answer for qustion (2)
1. One of the reasons why the MARE architecture is very inefficient is because it only has 1AC Assuming that you have access to many other ACs (AC, AC1, AC2, etc) Assume that in the new MARIE Architecture, you can do ADD 105 AC1 This means: Value @ x105 ACAC or suB 104 AC2 → This means: Valus @ x 104 + AC → AC2 How would your program (Lab #s, Question 1, also...
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