Question

2. (a) Briefly describe the compiler-based register optimization technique (typically (4 marks) (b) Describe the delayed branch technique and explain why it is more common in (4 marks) tetch, indirect and moon used for RISC machines). (c) Show the pipeline activity for the following code fragment with and without applying the delayed branch technique. Assume that there are three pipeline stages (fetch-decode, address calculation, data movement) for load and store RISC machines than in superscalar processors. instructions and two stages (fetch-decode, exccute) for ALU instructions Address Instruction Comment 100 LOAD RA,X X -RA LOAD RB,Y 101 102 ADD RA,RB RA RB >RA 103 104 JUMP 106 ADD RB, 1 STORE Y, RB RB> Y STORE X, RA 105 106 (10 marks) (d) Assume that, before the execution of the code, memory locations X and Y con- tain 1 and 2, respectively. What are their respective values after the execution of the code with and without applying the delayed branch technique? (2 marks)

Answer 1

Answer 2.(a) A small number of registers (e.g. 16-32) is available on the target RISC machine and the concept of registers window can not be used. In this case, optimized register usage is the responsibility of the compiler.

A program written is a high level language has no explicit references to registers. The objective of the compiler is to keep the operands for as many computations as possible in registers rather than main memory, and to minimize load and store operations.

To optimize the use of registers, the approach taken is as follows:

Each program quantity that is a candidate for residing in a register is assigned to a symbolic or virtual register.

The compiler then maps the unlimited number of symbolic registers into a fixed number of real registers.

Symbolic registers whose usage does not overlap can share the same real register.

If in a particular portion of the program, there are more quantities to deal with than real registers, then some of the quantities are assigned to the memory location.

The task of optimization is to decide which quantities are to be assigned to registers at any given point of time in the program. The technique most commonly used in RISC compiler is known as graph coloring.

Answer 2(b) Delayed branch is used to reduce the branch/jump problem in the pipeline. It is a conditional branch instruction found in some RISC architectures that include pipelining. The effect is to execute one or more instructions following the conditional branch before the branch is taken. This avoids stalling the pipeline while the branch condition is evaluated, thus keeping the pipeline full and minimizing the effect of conditional branches on processor performance.

RISC architecture enables to execute instructions in parallel. In parallel computing, the tasks are broken down into definite units. Each unit is further divided into sets of instructions. These instructions execute in parallel (simultaneously) on multiple CPUs. It is more difficult to program a parallel system than a single processor system, as the architecture of different parallel systems may vary, and the processes of multiple processors must be synchronized and coordinated.

That's why delayed branch technique is more common in RISC