Question

Consider the following assembly code. 1. 1, LOAD R, #1 2, LOADS, #1 3, LOAD T, #(k-3) 4. ADD AC, R, S 5. LOAD R, S 6. LOAD S, AC 8. BRP 4, T 9. STOR AC, M where R, S, T, AC are is addressing and BRP stands for "branch if positive". sters, M is a memory location, # indicates immediate (a) Explain what this code computes (assuming that k is a natural number greater than two). (6 marks) (b) Explain the effect of the branch instruction on performance when the code is executed on a pipelined processor. (6 marks) Explain how a RISC machine would minimize the number of delay slots (c) (8 marks)

Answer 1

(a) Load value at index address of 1 into R.

Load value at index address of 1 into S.

Load value at index address of (k-3) into T(based on the value of k).

Add R and S and store them into AC.

Load value from S into R.

Load value from AC into S.

Decrement T.

Loop until T reaches 0 value and if the accumulator reaches 0 pc(program counter) will be set to given address 4.

Store AC into memory location M.

(b) Unless the processor can give effect to the branch in a single time cycle, the pipeline will continue fetching instructions sequentially. Such instructions cannot be allowed to take effect because the programmer has diverted control to another part of the program. So a branch out of the normal sequence often involves a hazard.

The processor in a conditional branch may or may not branch, depending upon a calculation that has not yet occurred which makes it even more problematic. Many different processors may begin to execute 2 different program sequences, both assuming the branch is and is not taken, discarding all work that pertains to incorrect guess.

A processor with the implementation of branch prediction that usually makes correct predictions can minimize the performance penalty from branching. However, if branches are predicted poorly, it may create more work for the processor such as flushing from the pipeline the incorrect code path.

Programs that are written for the pipelined processor deliberately avoid branching to minimize possible loss of speed.

(c) Branch delay slots are one of the features of RISC architectures. The RISC is known to be pipelined, so while the current instruction is in execution, the following instructions will be in pipeline already. If there is, for example, a conditional branch in the instruction stream, the CPU cannot know whether the next instruction is the one following the branch or the instruction at the target location until it has evaluated the branch. This would cause a bubble in the pipeline; therefore some RISC architectures have a branch delay slot. The instruction after the branch will always be executed, no matter whether the branch is taken or not.