Question

1.  The function L is defined as L(1) = 2,L(2) = 1,L(3) = 3,L(4) = 4 and for n ≥ 4,

L(n + 1) = L(n) + L(n − 1) + L(n − 2)

L(n − 3)

i.e., the (n + 1)-th value is given by the sum of the n-th, n − 1-th and n − 2-th values divided by the n − 3-th value.

(a)  Write an assembly program for computing the k-th value L(k), where k is an integer bigger than 4 and read from a memory location M , and storing L(k) at memory location M . Use the instruction set in the Instruction Set Architecture described in Appendix A.

(b)  Consider a pipelined processor, where the pipeline stages are those described in the appendix. Describe what happens in the pipeline stages for the various types (data movement, data processing, control) of instructions.

(c)  Show the execution of your program on the above pipelined processor for k = 6 by drawing a diagram. Assume that the fetched and decoded instructions are stored in an instruction window IW with unlimited capacity (and so you can store any number of instruction in the IW). Explain where and why delay slots appear. Assume that the processor can do out-of-order execution to speed up the completion of the program. Assume that there is only one bus, and that the fetching of instructions uses this bus. So the fetching of an instruction can conflict with a stage where an instruction accesses memory.

 

 

 

 

 

 

 

 

 

 

 

 

A.1        Instruction set

We present a list of instructions typical of a RISC (reduced instruction set computer) machine. In data-movement and control instructions, the addresses may be immediate #X, direct (memory) M, indirect (memory) [M], register r, or register indirect [r] addresses. Data-processing instructions use immediate or register addressing. PC is the programme counter and a <- b indicates that the value of b is placed in a.

 

 

LOAD a, b                    a <- b

STOR a, b                    a <- b

ADD a, b, c               a <- b + c

ASH a, b, c               a <- (b >>[s] c)

LSH a, b, c               a <- (b >>[u] c) BR a               PC <- a

 

SUB

a,

b,

c

a

<-

b

- c

BEQ

a,

b,

c

PC

<-

a

if

b =

c

MUL

a,

b,

c

a

<-

b

* c

BNE

a,

b,

c

PC

<-

a

if

not

b = c

DIV

a,

b,

c

a

<-

b

/ c

BLT

a,

b,

c

PC

<-

a

if

b <

c

AND

a,

b,

c

a

<-

b

& c

BGT

a,

b,

c

PC

<-

a

if

b >

c

 

OR a, b, c                 a <- b | c

NOT a, b                      a <- !b

BLE a, b, c               PC <- a if b <= c BGE a, b, c            PC <- a if b >= c

 

Note:  Here b >>[s]  c denotes the arithmetical shift of b to the right by c positions, and

b >>[u]  c denotes the logical shift of b to the right by c positions.

 

A.2       The pipeline

We will use a five-stage pipeline:

•   IF (instruction fetch),

•   ID (instruction decode),

•   RR (register read),

•   EX (execute instruction),

•   WB (write back result into register).

•   Note that for some instructions (e.g., LOAD r, #X) some of the pipeline stages (e.g., RR) are not needed.

 

 

 

 

A.3       Execution rules

The rules for the execution of instructions are as follows:

1.  All instructions go through the IF and ID stages

2.  For data-movement instructions the data transfer between the CPU and main mem- ory happens in the execute stage. (This means that if a data transfer operation is executing, no data can be transferred across the main-memory bus.)

3.  Immediate addressing for input arguments does not require RR or EX (e.g., LOAD r1, #X).

4.  Arithmetic and logic instructions need RR, EX and WB.

5.  Branching operations require RR, EX and WB, unless all operands are immediate, in which case only EX and WB are required.

6.  For the instruction LOAD a, b the argument b must be an immediate address or memory location and a must be a register.

7.  For the instruction STOR  a, b the argument b must be an immediate address or register and a must be a memory location.

8.  For each of the remaining instructions the arguments a, b and c must all be registers or immediate addresses.

You may assume for the sake of the assignment that the ISA supports floating point arithmetic with no loss of precision.