Question

T F Xilinx's SDK assembler supports both FOR statements, but not wHILE statements T F In the ARM processor, immediate operands are stored in data memory, and not in the opcode T F In ARM processor instructions, one but not both operands can come from main T F In the ARM processor, a single load/store instruction T F It is possible for a microprocessor to use a virtual TCache memory is typically much faster and much larger than main memory can access memory and update the base register memory system without also using cache memory / E/ The ARM includes 32 GPR's TFM TFO T F Modern (nor) flash read and write access times are under 100ns, making them fast enough to be u T F ost microprocessors use a single bus that is shared between DDR and SRAM on many processors, peripherals can assert a "hold" signal to insert wait states to extend bus cycles as main memory on many processons In the ARM processor, read and write FIFo's are mostly located inside the GIC The memory management unit's job is to ensure cache coherency The AXI bus is used by ARM to connect the processor on-board IP blocks AUART bus includes a clock signal that can be programmed to be high (CPOL-1) or low (CPOL-O In the ZYNQ device, the Global Timer module is most often used to create PWM signals A virtual memory system requires that virtual addresses are dynamically translated at run time An H-bridge circuit is commonly used to control a servo motor TF T F TF T F T F T F In a virtual memory system, object files (.elf files) must be loaded into main memory at preas physical addresses When booting the ARM, the address of the first executed instruction is specified in the vecto When programming the ARM using assembly, you must declare all data types The ARM uses an instruction pipeline to speed up execution Watchdog timers are used to generate an interrupt if the processor hangs A watchdog timer is typically reset automatically by hardware, without any software inter Most ALU status bits include a "T" bit to indicate whether the previous instruction was Tr In the ARM, R12 is sometimes called the "heap register" T F T F T F T F T F T F TF T F In ZYNQ, all timer/counter modules share the same 64-bit counter T F The GIC will not issue interrupts whose sources have a priority lower than the current C TF When IRQ is asserted, the ARM processor will only accept the interrupt if the ALU statu T F 12C data transfers are generally faster than SPI data transfers Because the 12C controller is synchronous, it cannot generate interrupts when new da F T

Answer 1

1. False

2. True

3. False

4. True

5. False

6. True

7. In ARMv6-M and ARMv7-M based processors, there are 30 (or 32 if Security Extensions are implemented) general-purpose 32-bit registers

8. True

9. True

10. False