Question

4) Consider the following assembly language code: INSTRUCTIONS T01 T02 T03 T04 T05 T06 T07 T08 T09 T10 T11 T12 T13 T14 (as a table)

Loop: sll $t1, $s3, 2

add $t1, $t1, $s6

lw $t0, 0($t1)

beq $t0, $s5, Exit

addi $s3, $s3, 1

j Loop Exit:

Use a pipeline with forwarding, hazard detection, and 1 delay slot for branches. The pipeline is the typical 5-stage IF, ID, EX, MEM, WB MIPS design. For the above code, complete the pipeline diagram below (instructions on the left, cycles on top) for the code. Insert the characters IF, ID, EX, MEM, WB for each instruction in the boxes. Assume that there two levels of bypassing, that the second half of the decode stage performs a read of source registers, and that the first half of the write-back stage writes to the register file.

Note which stage of the pipeline each instruction is in. Label and briefly explain all data stalls with an X. Label and briefly explain all data forwards with an arrow between the stages handing off the data and the stages receiving the data. What is the final execution time of the code?

Answer 1

1st forwarding takes place for register $t1 from EX stage of SLL instruction to EX stage of add instruction.

2nd forwarding takes place for register $t1 from EX stage of ADD instruction to EX stage of lw instruciton.

3rd forwarding takes place for register $t0 from MEM stage of lw instruction to EX stage of beq instruction. lw instruction cause 1 stall as data will be available only after memory access.

Final execution time = 11 cycles

Toi IF T08 109 110 111 T02 ID IF MEM sll $t1,$s3, 2. add $t1,$t1, $s6 lw $t0, 0($t1) beq $t0,$s5, Exit addi $s3, $s3, 1 j Loop T03 T04 105 106 107 EX MEM WB ID EX WB IF IDEX MEMWB IF D X EX IF X ID X IF MEM EX ID WB MEM EX WB MEM WB