c. The classic five-stage pipeline MIPS architecture is used to execute the code fragments. Assume the...
c. The classic five-stage pipeline MIPS architecture is used to execute the code fragments. Assume the followings:
- Register write is done in the first half of the clock cycle; register read is performed in the second half of the clock cycle,
- Branches are resolved in the second stage of the pipeline and the architecture does not utilize any branch prediction mechanism
- Forwarding is fully supported
|
Clock Cycle à |
1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
10 |
11 |
12 |
13 |
14 |
15 |
16 |
|
add R4, R5, R6 |
IF | ID | EX | MEM | WB | |||||||||||
|
lw R1, 0(R2) |
IF |
ID |
EX |
MEM |
WB |
|||||||||||
|
beq R1, R4, target |
IF |
stall |
stall |
ID |
EX |
MEM |
WB |
|||||||||
|
I4 |
IF |
ID |
EX |
MEM |
WB |
This is what I have so far, and I believe this is correct, but could someone please verify it, and if incorrect tell me why and where corrections should be made.
With it having Forwarding fully supported, I believe that cycle for the beq should be stalled, but it could also be that there are NO stall cycles and that the I4 instruction would end up looking like this table below. Please help
|
Clock Cycle à |
1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
10 |
11 |
12 |
13 |
14 |
15 |
16 |
|
add R4, R5, R6 |
IF | ID | EX | MEM | WB | |||||||||||
|
lw R1, 0(R2) |
IF |
ID |
EX |
MEM |
WB |
|||||||||||
|
beq R1, R4, target |
IF |
ID | EX | MEM | WB | |||||||||||
|
I4 |
IF |
ID | EX | MEM | WB |
Thank you
Homework Answers
As Forwarding is fully supported we can forward the EX stage result of the instruction "lw R1, 0(R2)" to the execute stage of the instruction 'beq R1, R4, target" without any stall in the pipeline. So the second diagram is correct.
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