Question

1. The latencies of individual stages in five-stage MIPS (Microprocessor without Interlocked Pipeline Stages) Architecture are given below.

Instruction	Instruction Fetch	Register Read	Arithmetic Logic Unit (ALU)	Memory Access	Register Write
Latency	200ps	100ps	200ps	300ps	100ps

a. (10 pts) What is the clock cycle time in a pipelined and non-pipelined processor?

Pipelined version : ______________

Non-pipelined version : ______________

b. The classic five-stage pipeline MIPS architecture is used to execute the code fragments. Assume the followings:

1. • Register write is done in the first half of the clock cycle; register read is performed in the second half of the clock cycle,
   • Branches are resolved in the fourth stage of the pipeline and the architecture does not utilize any branch prediction mechanism
   • Forwarding is not supported.

i. (5 pts) Assuming there is no dependence other than one(s) given in the code, show the pipeline diagram.

Clock Cycle ->	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16
add      R1, R2, R3
add      R4, R5, R6
beq      R1, R4, target
I4

Answer 1

a)

Pipelined Processor: Clock cycle time for a pipelined processor is determined the slowest stage i.e. it is equal to the time taken by the most time taking stage.

Non-Pipelined Processor: Clock cycle time for a non-pipelined processor is equal to the time taken by each stage.

Therefore,

Pipelined version: 300 ps

Non-Pipelined version: (200 + 100 + 200 + 300 + 100 ) ps = 900 ps

b)

Pipelined Diagram:

Clock Cycle ->

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

add      R1, R2, R3

IF

ID

EX

MEM

WB

add      R4, R5, R6

IF

ID

EX

MEM

WB

beq      R1, R4, target

IF

ID

EX

MEM

WB

I4

IF

ID

EX

MEM

WB

IF -> Instruction Fetch

ID -> Instruction Decode

EX -> Execute

MEM -> Memory

WB -> Write Back