Question

4.10 In this exercise, we examine how resource hazards, control hazards, and Instruction Set Architecture (ISA) design can affect pipelined execution. Problems in this exercise refer to the following fragment of MIPS code:

sw r16,12(r6)

lw r16,8(r6)

beq r5,r4,Label # Assume r5!=r4

add r5,r1,r4

slt r5,r15,r4

Assume that individual pipeline stages have the following latencies: (NOTE THESE ARE DIFFERENT VALUES THAN THE ONES IN OTHER SIMILAR QUESTIONS)

IF	ID	EX	MEM	WB
250ps	100ps	175ps	150ps	200ps

4.10.4 [10] <§4.5> Given these pipeline stage latencies, repeat the speedup

calculation from 4.10.2, but take into account the (possible) change in clock cycle

time. When EX and MEM are done in a single stage, most of their work can be

done in parallel. As a result, the resulting EX/MEM stage has a latency that is the

larger of the original two, plus 20 ps needed for the work that could not be done

in parallel.

Answer 1