Question

In this exercise, we examine how pipelining affects the clock cycle time of the processor. Problems in this exercise assume that individual stages of the datapath have the following latencies: IF | ID | EX | MEMIwB 200ps 400ps 150ps 250ps 200ps Also, assume that instructions executed by the processor are broken down as follows: alu beqIwSW 45% 20% 20% 15% 3.1 What is the clock cycle time in a pipelined and non-pipelined processor? 3.2 What is the total latency of an LW instruction in a pipelined and non-pipelined processor? 3.3 If we can split one stage of the pipelined datapath into two new stages, each with half the latency of the original stage, which stage would you split and what is the new clock cycle time of the processor?

Answer 1

3.1). clock cycle time in pipeline processor = max { IF latency,ID latency, EX latency,MEM latency,WB latency }

= max { 200,400,150,250,200 }

= 400 ps

Clock cycle time in non-pipeline processor = time take by one process in non-pipeline processor = sum of all stage latencies= 200 + 400 + 150 + 250 + 200 = 1200 ps

3.2).

suppose total number of instructions = x (i'm assuming it as 'x' because it is not mentioned in question)

Pipeline processor:-

Number of cycles per instructions in pipeline (CPI) = 1

so,total latency of the LW instructions in pipeline processor = number of cycles taken by one LW instructions * number of LW instructions * cycle time

= 1 * (0.2*x) * 400ps

= 80x ps

now, putting different value of x,we will get different total latency of LW instructions as it is not mentioned in question.

Non-Pipeline processor:-

here,clock cycle time = 1200 ps

so,total latency of LW instructions in non-pipelined processor = number of LW instructions * clock cycle time in non-pipeline

= 0.2*x * 1200 ps

= 240x ps

3.3). presently,before splittling,clock cycle time = 400 ps

It is 400 ps mainly because of ID stage which has latency of 400 ps.

so,if we want to reduce the clock cycle time in pipeline,we must split the ID stage into two new stages ID1 and ID2.

after splitting ID1 latency = 200 ps , ID2 latency = 200 ps

new clock cycle time = max { 200, 200,200,150,250,200 } = 250 ps

clearly,clock cycle time has reduced from 400 ps to 250 ps.