Question

1. Assume that individual stages of the datapath have the following latencies:

IF	ID	EX	MEM	WB
250 ps	350 ps	150 ps	300 ps	200 ps

Also, assume that instructions executed by the processor are broken down as follows:

alu	beq	lw	sw
45%	20%	20%	15%

1. What is the total latency of an ?w instruction in a pipelined and non-pipelined processor?
2. Instead of a single-cycle organization, we can use a multi-cycle organization where each instruction takes multiple cycles but one instruction finishes before another is fetched. In this organization, an instruction only goes through stages it actually needs (e.g., ST only takes 4 cycles because it does not need the WB stage). Compare clock cycle times and execution times with single cycle, multi-cycle, and pipelined organization.

Answer 1

Answer:-----------

a).
Total latency of lw instruction in a non-pipelined processor is equal to the clock cycle time:
===> 250 + 350 + 150 + 300 + 200 = 1250 ps.

Total latency of lw instruction in a pipelined processor is the clock cycle multiplied by the number of stages:
===> 350 x 5 = 1750 ps.

b).

	single cycle	multi-cycle	pipelined
clock cycle time	1280 ps	380 ps	380 ps
execution time (cycles)	5 X	3.9 X	~ X

Where X is the total number of instructions of the program and for pipe-lined, we assume no data dependency and no stalls.

Answer 2

To calculate the total latency of an instruction in a pipelined and non-pipelined processor, we need to consider the latencies of each stage in the datapath and the breakdown of instructions executed by the processor.

Given the following latencies for each stage in the datapath: IF (Instruction Fetch): 250 ps ID (Instruction Decode): 350 ps EX (Execute): 150 ps MEM (Memory Access): 300 ps WB (Write Back): 200 ps

And the breakdown of instructions executed by the processor: ALU: 45% BEQ: 20% LW: 20% SW: 15%

Let's calculate the total latency for each organization:

1. Single-Cycle Organization: In a single-cycle organization, all instructions take the same amount of time to complete, regardless of their type. Therefore, the total latency for any instruction is the sum of the latencies of all stages.

Total latency for an instruction = IF + ID + EX + MEM + WB = 250 ps + 350 ps + 150 ps + 300 ps + 200 ps = 1250 ps

2. Multi-Cycle Organization: In a multi-cycle organization, each instruction takes a variable number of cycles based on its type. From the given breakdown, we can determine the number of cycles needed for each instruction type.

ALU: 45% of instructions = 0.45 * Total Instructions BEQ: 20% of instructions = 0.20 * Total Instructions LW: 20% of instructions = 0.20 * Total Instructions SW: 15% of instructions = 0.15 * Total Instructions

To determine the total latency, we multiply the number of cycles needed for each instruction type by the corresponding latencies of the stages involved.

Total latency for an instruction = (ALU cycles * (IF + ID + EX + MEM + WB)) + (BEQ cycles * (IF + ID + EX + MEM)) + (LW cycles * (IF + ID + EX + MEM + WB)) + (SW cycles * (IF + ID + EX + MEM))

Assuming the total instructions executed is 100 (for easy calculation purposes), we can substitute the percentages and calculate the total latency.

Total latency for an instruction = (0.45 * 100 * (250 + 350 + 150 + 300 + 200)) + (0.20 * 100 * (250 + 350 + 150 + 300)) + (0.20 * 100 * (250 + 350 + 150 + 300 + 200)) + (0.15 * 100 * (250 + 350 + 150 + 300))

Total latency for an instruction = 100,000 ps (or 100 ns)

3. Pipelined Organization: In a pipelined organization, multiple instructions can be in different stages simultaneously, overlapping their execution. However, the first instruction still experiences the full latency, while subsequent instructions benefit from pipeline parallelism.

Assuming an ideal pipeline without any stalls or hazards, the clock cycle time in a pipelined processor is determined by the longest stage latency, which is MEM (300 ps) in this case.

Clock cycle time in a pipelined processor = MEM latency = 300 ps

To calculate the total latency of an instruction, we can assume that each instruction takes the number of cycles equal to the number of stages it needs to pass through, including the WB stage.

Total latency for an instruction = MEM latency = 300 ps

Comparing the Clock Cycle Times and Execution Times:

1. Single-Cycle Organization: Clock cycle time