Question

In this exercise, we examine how pipelining affects the clock cycle time of the processor. Problems in this exercise assume that individual stages of the datapath have the following latencies: [17pts] 3. IF ID EEX MEM | WB 250ps 350ps 150ps300ps200ps a. what is the clock cycle time in a pipelined and non-pipelined (ie, single cycle) processor? what is the total latency of one lw instruction in a pipelined and non-pipelined (i.e., single cycle) processor? b. What is the total latency of executing 1000 1w instructions in a pipelined and non-pipelined processor (assume there are no data dependencies between the instructions)? What is the speedup achieved by using pipelining in this example? c. d. If you could split one stage of the pipelined datapath into two new stages, each with half the latency of the original stage, which stage would you split, and what is the new clock cycle time of the processor?

Answer 1

3.a

Pipelining: In pipelining, all the stages take a single clock cycle, so the clock cycle must be long enough to accommodate the slowest operation. Therefore, In pipeline the cycle time is determined by the slowest stage Instruction Decode (ID): 350 ps Non-Pipelining: In non-pipelining, each instruction goes through all the stages. Therefore, cycle time is determined by the sum of all the stages: Cycle time: 250+ 350 + 150+300+200 - 1,250 ps

3.b

3.c calculate same as above

3.d

Splitting the longest stage is the only way to reduce the cycle time. After splitting it, the new cycle time is based on the new longest stage a. Old longest stage is Instruction decode. Old CT-350 ps. b. New longest stage is Memory. New CT- 300 ps.