Question

2 This exercise is intended to help you understand the relationship between forwarding hazard detection, and ISA design. Problems in this exercise refer to the following sequence of instructions, and assume that it is executed on a 5-stage pipelined datapath: lw r5,4(r5) add r5,r2,r5 Iw r3,0(r5) or r3,r5,r3 sw r4,0(r5) 2.1 If there is no forwarding or hazard detection, how many nops needed to be inserted to ensure correct execution, and how many cycles needed to execute the codes? 2.2 If the processor has full forwarding and hazard detection, how many nops still needed to be inserted to ensure correct execution, and how many cycles needed to execute the codes? 2.3 If the processor has forwarding, but we forgot to implement the load-use hazard detection unit, what happens when this code executes? 2.4 If there is forwarding, for the first five cycles during the ex ecution of this code, specify which signals are asserted in each cycle by hazard detection and forwarding units in the following Figure 4.60 (PCWrite, IF/IDWrite, Forward_A, and Forward_B) Hazard ID/EX.MemRead detection unit ID/EX wBi EXMEM WB Control M MEM/WB Registers ALU Instruction Data memory memory IFAD RegisterRs IF1D Registerft IFID RegisterR IF/ID RegisterRd IDEX RegisterRI Forwarding unit MUX

Answer 1

PFB link as an answer to your question.

Refer to exercise no 14.3 as solution to your answer. The answer has been well explained with all the details given out. Reach through the comment section for ant further understanding of the concept.

https://drive.google.com/open?id=1zQPHibvM9yqy5teP8XHfExDOcyrRdl-9