Question

2 This exercise is intended to help you understand the relationship between forwarding hazard detection, and ISA design. Problems in this exercise refer to the following sequence of instructions, and assume that it is executed on a 5-stage pipelined datapath: w r5,4(r5) add r5,r2,r5 w r3,0(r5) or r3,r5,r3 sw r4,0(r5) 2.1 If there is no forwarding or hazard detection, how many nops needed to be inserted to ensure correct execution, and how many cycles needed to execute the codes? 2.2 If the processor has full forwarding and hazard detection, how many nops still needed to be inserted to ensure correct execution, and how many cycles needed to execute the codes? 2.3 If the processor has forwarding, but we forgot to implement the load-use hazard detection unit, what happens when this code executes? 2.4 If there is forwarding, for the first five cycles during the execution of this code, specify which signals are asserted in each cycle by hazard detection and forwarding units in the following Figure 4.60 (PCWrite, IF/IDWrite, Forward_A, and Forward_B) Hazard detection unit IDEX.MemRead ID/EX wek EXMEM We Control M MEMWB IFID wB M EX Registers ALU Instruction memory Data memory IFAD Register AO Registerfit FID Registerit FID RegisterRd IDEX Registerf Forwarding unit IF/OWte

Answer 1

as HOMEWORKLIB RULES rule we CAN  SLOVE ONLY FIRST QUESTION