Question

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QUESTION 2 The pipeline in the ARMI1 CPU is shown in Figure Q2(a). There are three possible (a) paths through the pipeline. The path of the execution depends on what type of instruction is executing (b) Instruction Fetoh Write Decode Execute Back Address DCI Dcz WBIS FE1 FE2 Decode Issue Shif ALU Saturate WBes MAC2 МАСI МАСУ Figure Q2(a) (i) Identify the number of stages for the ARMI1 CPU pipelines. [1 mark] (ii) Previously, 3- and 4-stage pipelines were state of the art. Many of the current Intel processors have pipelines with 20 stages or more. Consider the reason why there are different number of stages in the pipeline implementation. [2 marks A processor has a four-stage pipeline: instruction fetch (FI), decode instruction and calculate address (DA), fetch operand (FO), and execute (EX). The processor is running a sequence of instruction as shown in Table Q2(b) Table Q2(b) Line Label Instruction RI-R1+1 R2 R2 +2 2 JUMP L6 R4 R4 +4 4 R5- R5 +5 R6- R6+6 L6: 6 END 7 Create the timing diagram (as in Table Q2(b)i) ) to show how many time units are needed for a processor with the 4-stage pipelining Table Q2(b)(i) Time 2 FI 1 3 4 5 6 Instruction 1 DA FO EX Instruction 2 Instruction 3 17 marks (i) Explain what happened to Instruction 4 during the implementation. [2 marks] (iii) Classify the pipeline hazard that occurred when JUMP instruction is implemented. Explain your answer. [2 marks] (iv) Recommend TWo (2) mechanisms to mitigate the impact of the pipeline hazards. [2 marks (c) A superscalar execution issues more than one instruction for execution at the same time. Using a similar timing diagram as in Table Q2(b)(i), evaluate the performance of the superscalar execution when compared to the 4-stage pipelining implementation. [4 marks] (d) Based on your findings in Question 2(b) and Question 2(c), recommend the best implementation of the instructions. Deduce your answer in terms of execution time and the transistor logic [5 marks]

Answer 1

2. b) i) The number of stages are 8 namely FE1, FE2, Decode, Issue, 3 stages of Execution and Write Back.

        ii) The instruction throughput of the processor is increased by implementing more pipelines. The more pipeline stages a processor has, the more instructions it can process simultaneously and the less is the latency between completed instructions. Thus a 20-stage pipeline performs better than a 3-stage or 4-stage pipeline.

2. c) i)

	1	2	3	4	5	6	7	8	9
Instruction 1	FI	DA	FO	EX
Instruction 2		FI	DA	FO	EX
Instruction 3			FI	DA	EX
Instruction 4				FI	DA
Instruction 5					FI
Instruction 6						FI	DA	FO	EX
Instruction 7							FI	DA	E

     

ii) Instruction 4 was fetched while instruction 3 was being decoded. In the next time interval, instruction 3 was executed while instruction 4 was decoded, as per the pipeline. On execution of instruction 3, control moves to instruction 6 irrespective of the status of the next instructions in the pipeline.

      iii) When the JUMP instruction is implemented, a branch hazard occurs in the pipeline. By the time instruction 3 is executed, instruction 4 is already decoded and instruction 5 has been fetched. Thus instruction 6 is not executed immediately after instruction 3, as should have been the case. This problem is known as the pipeline branch hazard.

      iv) Two mechanisms to mitigate the impact of the branch hazards are:

               a. Branch prediction- a prediction is made based on past records as to whether a instruction will jump to another instruction or not. If the prediction is correct, the problem is resolved otherwise it persists.

               b. Delayed branching- when the branch instruction completes execution, the instructions already in the pipeline are allowed to go to completion. The next instruction to be fetched is the branched instruction and all intermediate instructions are ignored.