Question

The following MIPS program is to be run on a MIPS pipeline processor of 5 stages...

The following MIPS program is to be run on a MIPS pipeline processor of 5 stages (IF-ID-EX-MEM-WB). Work out and diagram the optimal pipeline schedule using full forwarding from EX or MEM stages to any other stage, Draw the pipeline execution diagram for this code and then compute the pipeline CPI:
addi $t6, $t6, 10
sub $t5, $t6, $t4
srl $t5, $t5, 2
sw $t5, 20($t5)
lw $t2, 0($t6)
add $t7, $t2, $t3
beq $t5, $t7, End

0 0
Add a comment Improve this question Transcribed image text
Know the answer?
Add Answer to:
The following MIPS program is to be run on a MIPS pipeline processor of 5 stages...
Your Answer:

Post as a guest

Your Name:

What's your source?

Earn Coins

Coins can be redeemed for fabulous gifts.

Not the answer you're looking for? Ask your own homework help question. Our experts will answer your question WITHIN MINUTES for Free.
Similar Homework Help Questions
  • Ch04.2. [3 points] Consider the following assembly language code: I0: ADD R4 R1RO I1: SUB R9R3 R4...

    Ch04.2. [3 points] Consider the following assembly language code: I0: ADD R4 R1RO I1: SUB R9R3 R4; I2: ADD R4 - R5+R6 I3: LDW R2MEMIR3100]; 14: LDW R2 = MEM [R2 + 0]; 15: STW MEM [R4 + 100] = R3 ; I6: AND R2R2 & R1; 17: BEQ R9R1, Target; I8: AND R9 R9&R1 Consider a pipeline with forwarding, hazard detection, and 1 delay slot for branches. The pipeline is the typical 5-stage IF, ID, EX, MEM, WB MIPS...

  • MIPS Insertion program.........I could really use some help ASAP

    I have this MIPS program and I'm having trouble with it. This program is user inputs numbers until zero and sorts and print the numbers in order. Please soove this issue. You can use any sorting algorithm except bubble sort.  Need it as soon as possible. Here is the code:.datanum: .word 0space: .byte ' ' .text main:  # la $t0, val # loads val into a register  # li $t1, 0      #keeps track of how many numbers entered  la $a0,...

  • 1. Given the following instruction sequence for the MIPS processor with the standard 5 stage pipeline $10, S0. 4 addi lw S2.0(S10) add sw S2,4(510) $2, $2, $2 Show the data dependences between th...

    1. Given the following instruction sequence for the MIPS processor with the standard 5 stage pipeline $10, S0. 4 addi lw S2.0(S10) add sw S2,4(510) $2, $2, $2 Show the data dependences between the instructions above by drawing arrows between dependent instructions (only show true/data dependencies). a. Assuming forwarding support, in what cycle would the store instruction write back to memory? Show the cycle by cycle execution of the instructions as they execute in the pipeline. Also, show any stalls...

  • I need help plz 6. 4-stage MIPS pipeline: It has "IF, ID-EX, MEM, WB" stages. Specify...

    I need help plz 6. 4-stage MIPS pipeline: It has "IF, ID-EX, MEM, WB" stages. Specify how many stalls (or bubbles) are required for the following cases. Assume that there is a forwarding logic and branch condition is determined at ID-EX stage. No delayed branch is assumed. (a) lw $1, 4($0) add $2, $1, $1 (b) lw $1, 4($0) beq $1, $2, add $3, $4, $5 X: sub $3, $3, $5 7. For problem 2 (c), how many bubbles are...

  • (60 points) The following instructions are executed on the 5-stage MIPS pipelined datapath. add r...

    Computer architecture help: (60 points) The following instructions are executed on the 5-stage MIPS pipelined datapath. add r5,r2, r1 lw r3, 4(r5) lw r2, 0(r2) or r3, r5, r3 sw r3, 0(r5) (a) (20 points) List the data hazards in the above code. For each data hazard identified, clearly mark the source and the destination. For example you can say, there is a data hazard from instruction X to instruction Y on register Z. (b) (20 points) Assume there is...

  • 1. Suppose we have a 5-stage pipeline CPU and run the following instructions: or $tl, $t2, $t3 or...

    1. Suppose we have a 5-stage pipeline CPU and run the following instructions: or $tl, $t2, $t3 or $t2, $tl, $t4 or $tl, $tl, $t2 1.1. What dependencies are there in the code? 1.2. Suppose there is no forwarding. What hazard may happen? Draw the pipeline diagram and insert stall (nop) to prevent these hazard. 1.3. If the pipeline has full forwarding. Are there still hazard? If so, draw the pipeline diagram and insert stall (nop) to prevent the hazard....

  • c. The classic five-stage pipeline MIPS architecture is used to execute the code fragments. Assume the...

    c. The classic five-stage pipeline MIPS architecture is used to execute the code fragments. Assume the followings: Register write is done in the first half of the clock cycle; register read is performed in the second half of the clock cycle, Branches are resolved in the second stage of the pipeline and the architecture does not utilize any branch prediction mechanism Forwarding is fully supported Clock Cycle à 1 2 3 4 5 6 7 8 9 10 11 12...

  • a).For the following MIPS assembly code to be executed using the pipelined datapath, identify all of...

    a).For the following MIPS assembly code to be executed using the pipelined datapath, identify all of the data dependencies (which register in which instruction needs the result register value from which another instruction?) and enumerate them (give them numbers as 1,2, ...). b).Which dependencies are data hazards that will be resolved via forwarding and without a stall (you can specify the number(s) from the part a)? c).Which dependencies are data hazards that will cause a stall (you can specify the...

  • We have the following sequence of instructions in MIPS lw $t4, 4($s1) or $t1, $t2, $t3...

    We have the following sequence of instructions in MIPS lw $t4, 4($s1) or $t1, $t2, $t3 or $t2, $t1, $t4 or $t1, $t1, $t2 1) Indicate any hazards and what the hazard types are. 2) Assume there is no forwarding in this pipelined processor and each stage takes 1 cycle. Draw the pipeline chart and calculate how many cycles are consumed 3) Assume there is forwarding in this pipelined processor and each stage takes 1 cycle. Draw the pipeline chart...

  • 4) Consider the following assembly language code: INSTRUCTIONS T01 T02 T03 T04 T05 T06 T07 T08...

    4) Consider the following assembly language code: INSTRUCTIONS T01 T02 T03 T04 T05 T06 T07 T08 T09 T10 T11 T12 T13 T14 (as a table) Loop: sll $t1, $s3, 2 add $t1, $t1, $s6 lw $t0, 0($t1) beq $t0, $s5, Exit addi $s3, $s3, 1 j Loop Exit: Use a pipeline with forwarding, hazard detection, and 1 delay slot for branches. The pipeline is the typical 5-stage IF, ID, EX, MEM, WB MIPS design. For the above code, complete the...

ADVERTISEMENT
Free Homework Help App
Download From Google Play
Scan Your Homework
to Get Instant Free Answers
Need Online Homework Help?
Ask a Question
Get Answers For Free
Most questions answered within 3 hours.
ADVERTISEMENT
ADVERTISEMENT
ADVERTISEMENT