a)
Potential Hazards :-
RAW: Instructions 4 and 6. Register R0.
RAW: Instructions 5 and 6. Register R3.
b)
Hazards eleminated through stalling :-
Through forwarding :- (if forwarding enabled then no hazard )
Consider the following operations: A B- C The corresponding assembly code instruction list generated by a compiler are 1 load [%r0 +4], %r1 2 load [%r0 + 8], %r2 3 sub %r1, %r2,%r3 4 load [ZrO + 1...
Page 4 3. Pipeline is an instruction-level parallel processing techni microprocessor systems. The instruction throughput can be dramaticallu increased by this key technique. However, there are so called hazard problems. (a) Branch instruction will introduce problems to a pipelined instruction execution. Explain how this may happen in a DLX machine, and state ONE strategy that can be used to resolve the problem (6 marks) (b) Data hazards occur in instruction execution in a pipelined machine. () What is meant by...
a) Describe the main techniques used by superscalar processors to achieve a high degree of machine-level parallelism. Consider the following assembly code: I1: LOAD r3 (r1) TO 12: MOVE r4 #1 13: ADD r3 r3 r4 I4: LOAD r2 (r2) 15: MOVE r4 #2 I6: MUL r2 r2 r4 17: MUL r3 r3 r2 I8: LOAD r4 (r1) 19: MOVE r1 #3 I10: ADD r4 r4 r1 I11: MUL r3 r3 r4 Using register renaming reorganise the code from the...
Ch04.2. [3 points] Consider the following assembly language code: I0: ADD R4 R1RO I1: SUB R9R3 R4; I2: ADD R4 - R5+R6 I3: LDW R2MEMIR3100]; 14: LDW R2 = MEM [R2 + 0]; 15: STW MEM [R4 + 100] = R3 ; I6: AND R2R2 & R1; 17: BEQ R9R1, Target; I8: AND R9 R9&R1 Consider a pipeline with forwarding, hazard detection, and 1 delay slot for branches. The pipeline is the typical 5-stage IF, ID, EX, MEM, WB MIPS...
Question 2 ARM Assembly Language (25 marks) An ARM instruction set summary is provided at the end of this paper. (5 marks) Explain the difference between eor and eors instruction. Use an example to show why both forms are useful. а. b. (5 marks) Explain using an example what the "Idr r3, [r7,#4]" instruction does. c. (10 marks) The following is the assembly language generated by a C compile type mystery, %function mystery: args 0, pretend = 0, frame =...
2. a)Write the ARM ALP conditional code snippet for the following statements written in C-language. Assume R1 to Rn as06 variables Let R1, R2, R3 contain the starting addresses of arrays X, Y and Z respectively Use Register R4 for variable i. Display appropriate messages. While (i+10) else Z[i] XiYi; b)i Write a program to display a message "This is an examination Question" on the screen using 06 a function sub program Note the following Address of the string to...
Question 3. (10 points) Four resistors are connected as shown in Figure 28.9a Find the equivalent resistance between a and c. R1-16 and R4-12 Ω R2-13 R3-4 (a) (b) What is the current in each resistor if a potential difference of 0.64 V is maintained between a and c. Calculate the current in each resistor I (for Ri resistor)- I (for R2 resistor)- I (for R3 resistor) I (for R4 resistor)- Which resistor uses more power, R or R4? Which...
Consider the following assembly code. 1. 1, LOAD R, #1 2, LOADS, #1 3, LOAD T, #(k-3) 4. ADD AC, R, S 5. LOAD R, S 6. LOAD S, AC 8. BRP 4, T 9. STOR AC, M where R, S, T, AC are is addressing and BRP stands for "branch if positive". sters, M is a memory location, # indicates immediate (a) Explain what this code computes (assuming that k is a natural number greater than two). (6 marks)...
1.) a.) Using the simplified instruction set shown for part b, write code for the following. Suppose memory locations 1400 to 1449 contain 16-bit words. Each word represents 2 ASCII characters. Write code to read in and write out these 100 characters. Left-side character from location 1400 should be first, right-side character from location 1400 should be second, and remaining characters follow in numeric order. Assume you have access to 4 registers: R1, R2, R3, R4. Each register holds one...