[20 pts] 5- Consider the following hypothetical 1-address assembly instruction called "Store Accumulator Indirect with Post-increment"...
20 pts] 2- Consider the internal structure of the pseudo-CPU discussed in class augmented with a single-port register file (i.e., only one register value can be read at a time) containing 32 8-bit registers (RO-R31) and a Stack Pointer (SP). Suppose the pseudo-CPU can be used to implement the AVR instruction ICALL (Indirect Call to Subroutine) with the format shown below: 10001 10101 00001 10011 ICALL pushes the return address onto the stack and jumps to the 16-bit target address...
Question 4: Single Cycle Datapath Control (15 points) We wish to add the hardware support for a special R-type instruction jlr Jump and Link Register) to the single-cycle datapath below. Though this is an R-type instruction, but it is a special one that has the opcode being 000001 (instead of 000000), so the control unit will be able to differentiate this jlr instruction from the other R-type instructions and generate a special set of controls for this instruction. Opcode rs...
Question 5 0.25 pts What is the value of the MemWrite control signal? Question 6 0.25 pts What is the value of the ALUSrc control signal? Add Add Sum--(1 4 Shift left 1 Branch MemRead Instruction [6-0] ControMemtoReg MemWrite ALUSrc RegWrite Instruction [19-15]Read Read register 1 Read Read data! PCaddress Instruction [24-20] Zero ALU ALU result register 2 Instruction 31-0 Instruction [11-7 Read1 Address data | Write Read register daiaALU | M Instruction memory Write data Registers Write Data data...
Group Project 1 The Micro-1 Processor Simulation <Micro-1 Computer> Here's the organization of a computer equipped with a Micro-1 processor Memory contains an array of integer cells: int cell[] = new int[CAP]; where CAP is the capacity of memory. Initially this is set to 256. Internally, the Micro-1 processor is equipped with eight 32-bit data/address registers and two 32 bit control registers: PC, the program counter, contains the address of the next instruction to execute. IR, the instruction register, contains...