Question

20 pts] 2- Consider the internal structure of the pseudo-CPU discussed in class augmented with a single-port register file (i.e., only one register value can be read at a time) containing 32 8-bit registers (RO-R31) and a Stack Pointer (SP). Suppose the pseudo-CPU can be used to implement the AVR instruction ICALL (Indirect Call to Subroutine) with the format shown below: 10001 10101 00001 10011 ICALL pushes the return address onto the stack and jumps to the 16-bit target address contained in the Z register. Give the sequence of microoperations required to Fetch and Execute AVR's ICALL instruction. Your solutions should result in exactly 6 cycles for the fetch cycle and 8 cycles for the execute cycle. Assume the memory is organized into addressable bytes (i.e., each memory word is a byte), MDR is 8 bits, and AC, SP, PC, IR, and MAR are 16 bits. Also, assume Internal Data Bus is 16-bit wide, and thus can handle 8-bit or 16-bit (as wel as portion of 8-bit or 16-bit) transfers in one microoperation and SP has the capability to increment/decrement itself Clearly state any other assumptions made. ALU Register File R31- RO SP AC Internal Data Bus IR PC MDR MAR Internal Tolfrom memory and l/O devices CU signals External Control signals

Answer 1