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A block diagram of MIPS architecture is given below. What is the value of the control bit for each MUX during the execution oInstruction MUX 1 MUX 2 MUX 3 MUX 4 1w R1, 8 (R2) 1 N/A 0 0 add R1, R2, R3 N/A 0 X х ori R1, R2, 15 0 0 X X bne R1, R2, loop

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Answer #1

Instruction: lw R1, 8(R2)
MUX1 = 0
MUX2 = 1
MUX3 = 1
MUX4 = 0

Instruction: add R1, R2, R3
MUX1 = 1
MUX2 = 0
MUX3 = 0
MUX4 = 0

Instruction: ori R1, R2, 15
MUX1 = 0
MUX2 = 1
MUX3 = 0
MUX4 = 0

Instruction: bne R1, R2, loop
MUX1 = N/A
MUX2 = 0
MUX3 = N/A
MUX4 = 0

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