Question

Question 21 1 pts A 1.5 V digital system contains CMOS inverters driving 5 pF capacitive loads, and requires a maximum voltage fluctuation of no more than 0.25 V for correct operation. The power supply has an effective inductance of 100 pH, and there may be as many as 100 gates switching states in a time of 175 ps. What is worst-case voltage fluctuation expected, if all 100 gates attempt to change state at the same time? 0.5 V O 1.0 V O 1.5 V more than 1.5 V

Answer 1

21. The worst case voltage fluctuation expected, if all 100 gates attempt to change state at the same time is 1.5V.

22. The minimum value of additional decoupling capacitance required to reduce the voltage fluctuations to the desired range is 2nF.