Question

Goals: To learn general-purpose register architectures. To learn encoding an instruction set. Questions: 100 points: (1) 30 points, (2) 70 points 1. (30 points) The design of MIPS provides for 32 general-purpose registers and 32 floating-point registers. If registers are good, are more registers better? List and discuss as many trade-offs as you can that should be considered by instruction set architecture designers examining whether to, and how much to increase the numbers of MIPS registers. 2. [70 points] Consider the case of a processor with an instruction length of 12 bits and with 32 general purpose registers so the size of the address fields is 5 bits. 2.1 (35points) Is it possible to have instruction encodings for the following? You must provide encoding details to explain your answers. 3 two-address instructions 30 one-address instructions 45 zero address instructions 2.2 [35points] Is it possible to have instruction encodings for the following? You must provide encoding details to explain your answers. 3 two-address instructions 31 one-address instructions 35 zero address instructions . HINTS: 1. In 2.1 and 2.2, are we allowed to assume that all of the bits not used for the register addresses can be dedicated to the opcode? For example, is it accurate to say that a zero address instruction has a 12-bit opcode, allowing for 212 different instruction encodings (247 for one address instructions, etc)? Answer: Yes. all bits not used for register names are dedicated to opcode.

Answer 1

There are multiple questions and student didn't specified the particular one so according to HOMEWORKLIB RULES i have to attempt atleast one question so i have attempted 2nd question.Please give thumbs up if you like it

Step 1 :-

This concept basically belongs to the expand opcode technique and let us first discuss about it then come to the question

Steo 2 Encoding process